View LTC3703EGN-5_1983854.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc3703-5 1 37035f applicatio s u descriptio u features typical applicatio u , ltc and lt are registered trademarks of linear technology corporation. n high voltage operation: up to 60v n large 1 w gate drivers (with 5v supply) n no current sense resistor required n step-up or step-down dc/dc converter n dual n-channel mosfet synchronous drive n excellent transient response and dc line regulation n programmable constant frequency: 100khz to 600khz n 1% reference accuracy n synchronizable up to 600khz n selectable pulse skip mode operation n low shutdown current: 25 m a typ n programmable current limit n undervoltage lockout n programmable soft-start n 16-pin narrow ssop and 28-pin ssop packages the ltc ? 3703-5 is a synchronous step-down switching regulator controller that can directly step-down voltages from up to 60v, making it ideal for telecom and automotive applications. the ltc3703-5 drives external logic level n-channel mosfets using a constant frequency (up to 600khz), voltage mode architecture. a precise internal reference provides 1% dc accuracy. a high bandwidth error amplifier and patented* line feed forward compensation provide very fast line and load transient response. strong 1 w gate drivers allow the ltc3703-5 to drive multiple mosfets for higher current applications. the operating frequency is user program- mable from 100khz to 600khz and can also be synchro- nized to an external clock for noise-sensitive applications. current limit is programmable with an external resistor and utilizes the voltage drop across the synchronous mosfet to eliminate the need for a current sense resistor. for applications requiring up to 100v operation, refer to the ltc3703 data sheet. 60v synchronous switching regulator controller efficiency vs load current high efficiency high voltage step-down converter ltc3703-5 mode/sync fset comp fb i max inv run/ss gnd v in boost tg sw v cc drv cc bg bgrtn 22 f 2 1000pf 2200pf 10k 100 113k 1% 21.5k 1% 10 12k 30k 0.1 f v in 6v to 60v 8 h d1 mbr1100 v out 5v 5a 270 f 16v mmdl770t1 v cc 5v 0.1 f 37035 ta04 10 f 1 f + + + si7850dp si7850dp 22 f 470pf load current (a) 0 efficiency ( % ) 100 95 90 85 80 4 37053 ta04b 1 2 3 5 v in = 12v v in = 42v v in = 24v n 48v telecom and base station power supplies n networking equipment, servers n automotive and industrial control parameter ltc3703-5 ltc3703 maximum v in 60v 100v mosfet gate drive 4.5v to 15v 9.3v to 15v v cc uv + 3.7v 8.7v v cc uv C 3.1v 6.2v *u.s. patent numbers: 5408150, 5055767, 6677210, 5847554, 5481178, 6304066, 6580258; others pending.
ltc3703-5 2 37035f supply voltages v cc , drv cc .......................................... C0.3v to 15v (drv cc C bgrtn), (boost C sw) ...... C0.3v to 15v boost (continuous) ............................ C0.3v to 85v boost (400ms) ................................... C0.3v to 95v bgrtn ...................................................... C5v to 0v v in voltage (continuous) .......................... C0.3v to 70v v in voltage (400ms) ................................. C0.3v to 80v sw voltage (continuous) ............................ C1v to 70v sw voltage (400ms) ................................... C1v to 80v run/ss voltage .......................................... C0.3v to 5v absolute axi u rati gs w ww u (note 1) electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = drv cc = v boost = v in = 5v, v mode/sync = v inv = v sw = bgrtn = 0v, run/ss = i max = open, r set = 25k, unless otherwise specified. symbol parameter conditions min typ max units v cc , drv cc v cc , drv cc supply voltage l 4.1 15 v v in v in pin voltage l 60 v i cc v cc supply current v fb = 0v l 1.7 2.5 ma run/ss = 0v 25 40 m a i drvcc drv cc supply current (note 5) 0 5 m a run/ss = 0v 0 5 m a i boost boost supply current (note 5) l 360 500 m a run/ss = 0v 0 5 m a mode/sync, inv voltages ....................... C0.3v to 15v f set , fb, i max , comp voltages ................... C0.3v to 3v driver outputs tg ................................ sw C 0.3v to boost + 0.3v bg ........................... bgrtn C 0.3v to drv cc + 0.3v peak output current <10 m s bg,tg ............................ 5a operating temperature range (note 2) .. C40 c to 85 c junction temperature (notes 3, 7) ....................... 125 c storage temperature range ................. C65 c to 150 c lead temperature (soldering, 10 sec.)................. 300 c order part number gn part marking t jmax = 125 c, q ja = 110 c/w 37035 LTC3703EGN-5 package/order i for atio uu w consult ltc marketing for parts specified with wider operating temperature ranges. order part number ltc3703eg-5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view g package 28-lead plastic ssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 boost tg sw nc nc nc nc v cc drv cc bg nc nc nc bgrtn v in nc nc nc nc mode/sync f set comp fb i max inv nc run/ss gnd top view gn package 16-lead narrow plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 mode/sync f set comp fb i max inv run/ss gnd v in b00st tg sw v cc drv cc bg bgrtn t jmax = 125 c, q ja = 100 c/w
ltc3703-5 3 37035f note 1 : absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2 : the ltc3703-5 is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: ltc3703-5: t j = t a + (p d ? 100 c/w) g package note 4 : the ltc3703-5 is tested in a feedback loop that servos v fb to the reference voltage with the comp pin forced to a voltage between 1v and 2v. electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = drv cc = v boost = v in = 5v, v mode/sync = v inv = v sw = bgrtn = 0v, run/ss = i max = open, r set = 25k, unless otherwise specified. note 5: the dynamic input supply current is higher due to the power mosfet gate charging being delivered at the switching frequency (q g ? f osc ). note 6 : guaranteed by design. not subject to test. note 7 : this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125 c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 8 : r ds(on) guaranteed by correlation to wafer level measurement. symbol parameter conditions min typ max units main control loop v fb feedback voltage (note 4) 0.792 0.800 0.808 v l 0.788 0.812 v d v fb, line feedback voltage line regulation 5v < v cc < 15v (note 4) l 0.007 0.05 %/v d v fb, load feedback voltage load regulation 1v < v comp < 2v (note 4) l 0.01 0.1 % v mode/sync mode/sync threshold mode/sync rising 0.75 0.8 0.87 v d v mode/sync mode/sync hysteresis 20 mv i mode/sync mode/sync current 0 v mode/sync 15v 0 1 m a v inv invert threshold 1 1.5 2 v i inv invert current 0 v inv 15v 0 1 m a i vin v in sense input current v in = 60v 80 130 m a run/ss = 0v, v in = 10v 0 1 m a i max i max source current v imax = 0v 10.5 12 13.5 m a v os, imax v imax offset voltage |v sw | C v imax at i run/ss = 0 m a C 25 10 55 mv v run/ss shutdown threshold 0.7 0.9 1.2 v i run/ss run/ss source current run/ss = 0v 2.3 3.8 5.3 m a maximum run/ss sink current |v sw | C v imax > 100mv 9 17 25 m a v uv undervoltage lockout v cc rising l 3.4 3.7 4.1 v v cc falling l 2.8 3.1 3.4 v hysteresis l 0.45 0.65 0.85 v oscillator f osc oscillator frequency r set = 25k w 270 300 330 khz f sync external sync frequency range 100 600 khz t on, min minimum on-time 200 ns dc max maximum duty cycle f < 200khz 89 93 96 % driver i bg, peak bg driver peak source current 0.75 1 a r bg, sink bg driver pull-down r ds, on (note 8) 1.2 1.8 w i tg, peak tg driver peak source current 0.75 1 a r tg, sink tg driver pull-down r ds, on (note 8) 1.2 1.8 w feedback amplifier a vol op amp dc open loop gain (note 4) 74 85 db f u op amp unity gain crossover frequency (note 6) 25 mhz i fb fb input current 0 v fb 3v 0 1 m a i comp comp sink/source current 5 10 ma
ltc3703-5 4 37035f typical perfor a ce characteristics uw efficiency vs input voltage efficiency vs load current load transient response v cc current vs v cc voltage v cc current vs temperature v cc shutdown current vs v cc voltage v cc shutdown current vs temperature reference voltage vs temperature normalized frequency vs temperature temperature ( c) ?0 40 ?0 0 60 100 20 40 80 temperature ( c) ?0 40 ?0 0 60 100 20 40 80 60 40 20 0 20 40 60 80 100 temperature ( c) normalized frequency 37035 g09 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 load current (a) 0 efficiency (%) 100 95 90 85 80 1234 37035 g02 5 v cc voltage (v) 0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 7.5 37035 g04 2.5 5 10 12.5 15 v cc current (ma) temperature ( c) ?0 40 ?0 0 v cc current (ma) 60 100 37035 g05 20 40 80 4 3 2 1 0 37035 g03 v cc current ( a) 37035 g07 35 30 25 20 15 10 5 0 reference voltage (v) 0.803 0.802 0.801 0.800 0.799 0.798 37035 g08 v out = 12v f = 250khz pulse skip enabled v in = 42v v in = 24v v out 50mv/div i out 2a/div v in = 50v v out = 12v 1a to 5a load step 50 s/div v fb = 0v v cc rising v cc = 5v comp = 1.5v v fb = 0v comp = 1.5v input voltage (v) 0 80 efficiency (%) 85 90 95 100 10 20 30 40 37035 g01 50 60 i out = 1a v out = 5v f = 250khz forced continuous i out = 5a v cc voltage (v) 0 0 v cc current ( a) 20 40 60 80 48 12 16 37035 g06 100 120 26 10 14 t a = 25 c (unless otherwise noted).
ltc3703-5 5 37035f peak source current (a) 1.2 1.1 1.0 0.9 0.8 37035 g10 temperature ( c) r ds(on) ( ) 37035 g11 drv cc /boost voltage (v) 0 2.5 7.5 10 12.5 peak source current (a) 3.0 2.5 2.0 1.5 1.0 0.5 0 5 37035 g12 15 60 40 20 0 20 40 60 80 100 60 40 20 0 20 40 60 80 100 temperature ( c) v cc = 5v v cc = 5v v cc = 5v |sw| voltage (v) 0 25 20 15 10 5 0 ? ?0 0.3 0.5 37035 g17 0.1 0.2 0.4 0.6 0.7 run/ss sink current ( a) run voltage (v) 0.5 max duty cycle (%) 100 90 80 70 60 50 40 30 20 10 0 ?0 2.5 37035 g18 1.0 1.5 2.0 3.0 i max = 0.3v temperature ( c) run/ss current ( a) 15735 g15 5 4 3 2 1 0 ?0 ?0 20 40 ?0 0 60 80 100 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 drv cc /boost voltage (v) 2.5 1.1 1.2 1.3 12.5 37035 g13 1.0 0.9 5 7.5 10 15 0.8 0.7 0.6 r ds(on) ( ) gate capacitance (nf) 0 rise/fall time (ns) 100 150 20 37035 g14 50 0 5 10 15 200 rise time fall time v cc = 5v v cc voltage (v) 0 0 run/ss pull-up current ( a) 1 2 3 4 5 2.5 57.510 37035 g16 12.5 15 typical perfor a ce characteristics uw driver peak source current vs temperature driver pull-down r ds(on) vs temperature driver peak source current vs supply voltage rise/fall time vs gate capacitance run/ss pull-up current vs temperature run/ss pull-up current vs v cc voltage run/ss sink current vs sw voltage max % dc vs run/ss voltage driver pull-down r ds(on) vs supply voltage
ltc3703-5 6 37035f typical perfor a ce characteristics uw i max current vs temperature % duty cycle vs comp voltage max % dc vs frequency and temperature shutdown threshold vs temperature t on(min) vs temperature i max source current ( a) 13 12 11 37035 g19 frequency (khz) max duty cycle (%) 37035 g21 100 95 90 85 80 75 70 0 200 400 500 100 300 600 700 temperature ( c) shutdown threshold (v) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 37035 g22 37035 g23 t on(min) (ns) 160 140 120 100 80 60 40 20 0 60 40 20 0 20 40 60 80 100 temperature ( c) 60 40 20 0 20 40 60 80 100 60 40 20 0 20 40 60 80 100 temperature ( c) 25 c ?5 c 90 c comp (v) 0.5 duty cycle (%) 100 80 60 40 20 0 0.75 1.00 1.25 1.50 37035 g20 1.75 2.00 v in = 10v v in = 50v v in = 25v
ltc3703-5 7 37035f mode/sync (pin 1/pin 6): pulse skip mode enable/sync pin. this multifunction pin provides pulse skip mode en- able/disable control and an external clock input for synchro- nization of the internal oscillator. pulling this pin below 0.8v or to an external logic-level synchronization signal disables pulse skip mode operation and forces continuous opera- tion. pulling the pin above 0.8v enables pulse skip mode operation. this pin can also be connected to a feedback resistor divider from a secondary winding on the inductor to regulate a second output voltage. f set (pin 2/pin 7): frequency set. a resistor connected to this pin sets the free running frequency of the internal os- cillator. see applications section for resistor value selec- tion details. comp (pin 3/pin 8): loop compensation. this pin is con- nected directly to the output of the internal error amplifier. an rc network is used at the comp pin to compensate the feedback loop for optimal transient response. fb (pin 4/pin 9): feedback input. connect fb through a resistor divider network to v out to set the output voltage. also connect the loop compensation network from comp to fb. i max (pin 5/pin 10): current limit set. the i max pin sets the current limit comparator threshold. if the voltage drop across the bottom mosfet exceeds the magnitude of the voltage at i max , the controller goes into current limit. the i max pin has an internal 12 m a current source, allowing the current threshold to be set with a single external resistor to ground. see the current limit programming section for more information on choosing r imax . inv (pin 6/pin 11): top/bottom gate invert. pulling this pin above 2v sets the controller to operate in step-up (boost) mode with the tg output driving the synchronous mosfet and the bg output driving the main switch. below 1v, the controller will operate in step-down (buck) mode. run/ss (pin 7/pin 13): run/soft-start. pulling run/ss be- low 0.9v will shut down the ltc3703-5, turn off both of the external mosfet switches and reduce the quiescent sup- ply current to 25 m a. a capacitor from run/ss to ground will control the turn-on time and rate of rise of the output voltage at power-up. an internal 4 m a current source pull- up at the run/ss pin sets the turn-on time at approximately 750ms/ m f. gnd (pin 8/pin 14): ground pin. bgrtn (pin 9/pin 15): bottom gate return. this pin con- nects to the source of the pull-down mosfet in the bg driver and is normally connected to ground. connecting a negative supply to this pin allows the synchronous mosfets gate to be pulled below ground to help prevent false turn-on during high dv/dt transitions on the sw node. see the applications information section for more details. bg (pin 10/pin 19): bottom gate drive. the bg pin drives the gate of the bottom n-channel synchronous switch mosfet. this pin swings from bgrtn to drv cc . drv cc (pin 11/pin 20): driver power supply pin. drv cc provides power to the bg output driver. this pin should be connected to a voltage high enough to fully turn on the external mosfets, normally 4.5v to 15v for logic level threshold mosfets. drv cc should be bypassed to bgrtn with a 10 m f, low esr (x5r or better) ceramic capacitor. v cc (pin 12/pin 21) : main supply pin. all internal circuits except the output drivers are powered from this pin. v cc should be connected to a low noise power supply voltage between 4.5v and 15v and should be bypassed to gnd (pin 8) with at least a 0.1 m f capacitor in close proximity to the ltc3703-5. sw (pin 13/pin 26): switch node connection to inductor and bootstrap capacitor. voltage swing at this pin is from a schottky diode (external) voltage drop below ground to v in . tg (pin 14/pin 27): top gate drive. the tg pin drives the gate of the top n-channel synchronous switch mosfet. the tg driver draws power from the boost pin and returns to the sw pin, providing true floating drive to the top mosfet. boost (pin 15/pin 28): top gate driver supply. the boost pin supplies power to the floating tg driver. the boost pin should be bypassed to sw with a low esr (x5r or better) 0.1 m f ceramic capacitor. an additional fast recovery schot- tky diode from drv cc to boost will create a complete float- ing charge-pumped supply at boost. v in (pin 16/pin 1): input voltage sense pin. this pin is con- nected to the high voltage input of the regulator and is used by the internal feedforward compensation circuitry to im- prove line regulation. this is not a supply pin . uu u pi fu ctio s (gn16/g28)
ltc3703-5 8 37035f fu ctio al diagra u u w 5 1 uvsd otsd chip sd 1v 3.2v 4 a run/ss bandgap sync detect over temp v cc uvlo osc % dc limit drive logic + + + + ext sync forced continuous + + + + + 0.8v mode/sync 3 comp 4 fb 16 15 14 13 11 10 9 6 12 v in v cc (<15v) inv pwm min max 0.76v 0.84v overcurrent 12 a 50mv i max r max boost tg sw drv cc bg bgrtn inv 8 gnd gn16 ot sd 0.8v reference internal 3.2v v cc uv sd 2 fset 37035 fd reverse current fb rset 5 c ss r2 r1 v cc c vcc d b c b v cc v in m1 m2 c out v out l1 inv operatio u (refer to functional diagram) the ltc3703-5 is a constant frequency, voltage mode controller for dc/dc step-down converters. it is designed to be used in a synchronous switching architecture with two external n-channel mosfets. its high operating volt- age capability allows it to directly step down input voltages up to 60v without the need for a step-down transformer. for circuit operation, please refer to the functional diagram of the ic and the circuit on the first page of this data sheet. the ltc3703-5 uses voltage mode control in which the duty ratio is controlled directly by the error amplifier output and thus requires no current sense resis- tor. the v fb pin receives the output voltage feedback and is compared to the internal 0.8v reference by the error amplifier, which outputs an error signal at the comp pin.
ltc3703-5 9 37035f operatio u (refer to functional diagram) when the load current increases, it causes a drop in the feedback voltage relative to the reference. the comp volt- age then rises, increasing the duty ratio until the output feedback voltage again matches the reference voltage. in normal operation, the top mosfet is turned on when the rs latch is set by the on-chip oscillator and is turned off when the pwm comparator trips and resets the latch. the pwm comparator trips at the proper duty ratio by compar- ing the error amplifier output (after being compensated by the line feedforward multiplier) to a sawtooth waveform generated by the oscillator. when the top mosfet is turned off, the bottom mosfet is turned on until the next cycle begins or, if pulse skip mode operation is enabled, until the inductor current reverses as determined by the reverse current comparator. max and min comparators ensure that the output never exceed 5% of nominal value by monitoring v fb and forcing the output back into regulation quickly by either keeping the top mosfet off or forcing maximum duty cycle. the operation of its other features fast transient response, outstanding line regulation, strong gate drivers, short-circuit protection, and shutdown/ soft-startare described below. fast transient response the ltc3703-5 uses a fast 25mhz op amp as an error am- plifier. this allows the compensation network to be opti- mized for better load transient response. the high bandwidth of the amplifier, along with high switching fre- quencies and low value inductors, allow very high loop crossover frequencies. the 800mv internal reference allows regulated output voltages as low as 800mv without exter- nal level shifting amplifiers. line feedforward compensation the ltc3703-5 achieves outstanding line transient re- sponse using a patented feedforward correction scheme. with this circuit the duty cycle is adjusted instantaneously to changes in input voltage, thereby avoiding unaccept- able overshoot or undershoot. it has the added advantage of making the dc loop gain independent of input voltage. figure 1 shows how large transient steps at the input have little effect on the output voltage. 20 s/div v out 50mv/div v out = 12v i load = 1a 25v to 60v v in step v in 20v/div i l 2a/div 37035 f01 figure 1. line transient performance strong gate drivers the ltc3703-5 contains very low impedance drivers capable of supplying amps of current to slew large mosfet gates quickly. this minimizes transition losses and allows paralleling mosfets for higher current applications. a 60v floating high side driver drives the top side mosfet and a low side driver drives the bottom side mosfet (see figure 2). they can be powered from either a separate dc supply or a voltage derived from the input or output voltage (see mosfet driver supplies section). the bot- tom side driver is supplied directly from the drv cc pin. the top mosfet drivers are biased from floating boot- strap capacitor c b , which normally is recharged during each off cycle through an external diode from drv cc when the top mosfet turns off. in pulse skip mode operation, where it is possible that the bottom mosfet will be off for an extended period of time, an internal counter guarantees that the bottom mosfet is turned on at least once every 10 cycles for 10% of the period to refresh the bootstrap capacitor. an undervoltage lockout keeps the ltc3703-5 shut down unless this voltage is above 4.1v. the bottom driver has an additional feature that helps minimize the possibility of external mosfet shoot-thru. when the top mosfet turns on, the switch node dv/dt pulls up the bottom mosfets internal gate through the miller capacitance, even when the bottom driver is holding the gate terminal at ground. if the gate is pulled up high enough, shoot-thru between the top side and bottom side
ltc3703-5 10 37035f operatio u mosfets can occur. to prevent this from occuring, the bottom driver return is brought out as a separate pin (bgrtn) so that a negative supply can be used to reduce the effect of the miller pull-up. for example, if a C2v supply is used on bgrtn, the switch node dv/dt could pull the gate up 2v before the v gs of the bottom mosfet has more than 0v across it. cycle control set to 0%. as c ss continues to charge, the duty cycle is gradually increased, allowing the output voltage to rise. this soft-start scheme smoothly ramps the output voltage to its regulated value, with no overshoot. the run/ss voltage will continue ramping until it reaches an internal 4v clamp. then the min feedback comparator is enabled and the ltc3703-5 is in full operation. when the run/ss is low, the supply current is reduced to 25 m a. current limit normal operation start-up 0v 4v 3v 1.4v 1v 0v power down mode minimum duty cycle output voltage in regulation ltc3703-5 enable min comparator enabled 37035 f03 run/ss soft-starts output voltage and inductor current shutdown v out v run/ss (refer to functional diagram) boost tg sw bg bgrtn drv cc drv cc ltc3703-5 m1 m2 + + v in c in v out c out d b c b l 37035 f02 0v to 5v figure 3. soft-start operation in start up and current limit figure 2. floating tg driver supply and negative bg return constant frequency the internal oscillator can be programmed with an exter- nal resistor connected from f set to ground to run between 100khz and 600khz, thereby optimizing component size, efficiency, and noise for the specific application. the internal oscillator can also be synchronized to an external clock applied to the mode/sync pin and can lock to a frequency in the 100khz to 600khz range. when locked to an external clock, pulse skip mode operation is automati- cally disabled. constant frequency operation brings with it a number of benefits: inductor and capacitor values can be chosen for a precise operating frequency and the feedback loop can be similarly tightly specified. noise generated by the circuit will always be at known frequencies. subharmonic oscillation and slope compensation, com- mon headaches with constant frequency current mode switchers, are absent in voltage mode designs like the ltc3703-5. shutdown/soft-start the main control loop is shut down by pulling run/ss pin low. releasing run/ss allows an internal 4 m a current source to charge the soft-start capacitor c ss . when c ss reaches 1v, the main control loop is enabled with the duty current limit the ltc3703-5 includes an onboard current limit circuit that limits the maximum output current to a user-pro- grammed level. it works by sensing the voltage drop across the bottom mosfet and comparing that voltage to a user- programmed voltage at the i max pin. since the bottom mosfet looks like a low value resistor during its on-time, the voltage drop across it is proportional to the current flowing in it. in a buck converter, the average current in the inductor is equal to the output current. this current also flows through the bottom mosfet during its on-time. thus by watching the drain-to-source voltage when the bottom mosfet is on, the ltc3703-5 can monitor the output current. the ltc3703-5 senses this voltage and inverts it to allow it to compare the sensed voltage (which becomes more negative as peak current increases) with a positive voltage at the i max pin. the i max pin includes a 12 m a pull-up, enabling the user to set the voltage at i max with a single resistor (r imax ) to ground. see the current limit programming section for r imax selection.
ltc3703-5 11 37035f for maximum protection, the ltc3703-5 current limit consists of a steady-state limit circuit and an instanta- neous limit circuit. the steady-state limit circuit is a g m amplifier that pulls a current from the run/ss pin propor- tional to the difference between the sw and i max voltages. this current begins to discharge the capacitor at run/ss, reducing the duty cycle and controlling the output voltage until the current regulates at the limit. depending on the size of the capacitor, it may take many cycles to discharge the run/ss voltage enough to properly regulate the output current. this is where the instantaneous limit circuit comes into play. the instantaneous limit circuit is a cycle-by-cycle comparator which monitors the bottom mosfets drain voltage and keeps the top mosfet from turning on whenever the drain voltage is 50mv above the programmed max drain voltage. thus the cycle-by-cycle comparator will keep the inductor current under control until the g m amplifier gains control. pulse skip mode the ltc3703-5 can operate in one of two modes select- able with the mode/sync pinpulse skip mode or forced continuous mode. pulse skip mode is selected when increased efficiency at light loads is desired. in this mode, the bottom mosfet is turned off when inductor current reverses to minimize the efficiency loss due to reverse current flow. as the load is decreased (see fig- ure 5), the duty cycle is reduced to maintain regulation until its minimum on-time (~200ns) is reached. when the load decreases below this point, the ltc3703-5 begins to figure 4. efficiency in pulse skip/forced continuous modes load (ma) 10 efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 100 1000 10000 37035 f04 forced continuous pulse skip mode v in = 42v v in = 12v v out = 5v v in = 12v v in = 42v skip cycles to maintain regulation. the frequency drops but this further improves efficiency by minimizing gate charge losses. in forced continuous mode, the bottom mosfet is always on when the top mosfet is off, allowing the inductor current to reverse at low currents. this mode is less efficient due to resistive losses, but has the advantage of better transient response at low currents, constant frequency operation, and the ability to maintain regulation when sinking current. see figure 4 for a com- parison of the effect on efficiency at light loads for each mode. the mode/sync threshold is 0.8v 7.5%, allow- ing the mode/sync to act as a feedback pin for regulating a second winding. if the feedback voltage drops below 0.8v, the ltc3703-5 reverts to continuous operation to maintain regulation in the secondary supply. figure 5. comparison of inductor current waveforms for pulse skip mode and forced continuous operation pulse skip mode forced continuous decreasing load current 37035 f05 operatio u (refer to functional diagram)
ltc3703-5 12 37035f the basic ltc3703-5 application circuit is shown on the first page of this data sheet. external component selection is de- termined by the input voltage and load requirements as explained in the following sections. after the operating frequency is selected, r set and l can be chosen. the operating frequency and the inductor are chosen for a desired amount of ripple current and also to optimize ef- ficiency and component size. next, the power mosfets and d1 are selected based on voltage, load and efficiency re- quirements. c in is selected for its ability to handle the large rms currents in the converter and c out is chosen with low enough esr to meet the output voltage ripple and transient specifications. finally, the loop compensation components are chosen to meet the desired transient specifications. operating frequency the choice of operating frequency and inductor value is a trade off between efficiency and component size. low frequency operation improves efficiency by reducing mosfet switching losses and gate charge losses. how- ever, lower frequency operation requires more induc- tance for a given amount of ripple current, resulting in a larger inductor size and higher cost. if the ripple current is allowed to increase, larger output capacitors may be required to maintain the same output ripple. for convert- ers with high step-down v in to v out ratios, another consideration is the minimum on-time of the ltc3703-5 (see the minimum on-time considerations section). a final consideration for operating frequency is that in applicatio s i for atio wu uu noise- sensitive communications systems, it is often de- sirable to keep the switching noise out of a sensitive frequency band. the ltc3703-5 uses a constant frequency architecture that can be programmed over a 100khz to 600khz range with a single resistor from the f set pin to ground, as shown in the circuit on the first page of this data sheet. the nominal voltage on the f set pin is 1.2v, and the current that flows from this pin is used to charge and discharge an internal oscillator capacitor. the value of r set for a given operating frequency can be chosen from figure 6 or from the following equation: rk f khz set () () w= 7100 25 buck or boost mode operation the ltc3703-5 has the capability of operating both as a step-down (buck) and step-up (boost) controller. in boost mode, output voltages as high as 60v can be tightly regulated. with the inv pin grounded, the ltc3703-5 operates in buck mode with tg driving the main (top side) switch and bg driving the synchronous (bottom side) switch. if the inv pin is pulled above 2v, the ltc3703-5 operates in boost mode with bg driving the main (bottom side) switch and tg driving the synchronous (top side) switch. internal circuit operation is very similar regardless of the operating mode with the following exceptions: in boost mode, pulse skip mode operation is always dis- abled regardless of the level of the mode/sync pin and the line feedforward compensation is also disabled. the overcurrent circuitry continues to monitor the load current by looking at the drain voltage of the main (bottom side) mosfet. in boost mode, however, the peak mosfet current does not equal the load current but instead i d = i load /(1 C d). this factor needs to be taken into account when programming the i max voltage. frequency (khz) r set (k ) 1000 37035 f06 10 1 100 200 1000 800 600 400 0 figure 6. timing resistor (r set ) value operatio u (refer to functional diagram)
ltc3703-5 13 37035f the oscillator can also be synchronized to an external clock applied to the mode/sync pin with a frequency in the range of 100khz to 600khz (refer to the mode/sync pin section for more details). in this synchronized mode, pulse skip mode operation is disabled. the clock high level must exceed 2v for at least 25ns. as shown in figure 7, the top mosfet turn-on will follow the rising edge of the external clock by a constant delay equal to one- tenth of the cycle period. ripple current occurs at the highest v in . to guarantee that ripple current does not exceed a specified maximum, the inductor in buck mode should be chosen according to: l v fi v v out lmax out in max 3 d ? ? ? ? () () 1 the inductor also has an affect on low current operation when pulse skip mode operation is enabled. the fre- quency begins to decrease when the output current drops below the average inductor current at which the ltc3703-5 is operating at its t on(min) in discontinuous mode (see figure 5). lower inductance increases the peak inductor current that occurs in each minimum on-time pulse and thus increases the output current at which the frequency starts decreasing. power mosfet selection the ltc3703-5 requires at least two external n-channel power mosfets, one for the top (main) switch and one or more for the bottom (synchronous) switch. the number, type and on resistance of all mosfets selected take into account the voltage step-down ratio as well as the actual position (main or synchronous) in which the mosfet will be used. a much smaller and much lower input capaci- tance mosfet should be used for the top mosfet in applications that have an output voltage that is less than 1/3 of the input voltage. in applications where v in >> v out , the top mosfets on resistance is normally less impor- tant for overall efficiency than its input capacitance at operating frequencies above 300khz. mosfet manufac- turers have designed special purpose devices that provide reasonably low on resistance with significantly reduced input capacitance for the main switch application in switch- ing regulators. selection criteria for the power mosfets include the on resistance r ds(on) , input capacitance, breakdown voltage and maximum output current. the most important parameter in high voltage applica- tions is breakdown voltage bv dss . both the top and bottom mosfets will see full input voltage plus any additional ringing on the switch node across its drain-to- source during its off-time and must be chosen with the 37035 f07 2v to 10v mode/ sync tg i l t min = 25ns 0.8t 0.1t d = 40% t t = 1/f o applicatio s i for atio wu uu figure 7. mode/sync clock input and switching waveforms for synchronous operation inductor the inductor in a typical ltc3703-5 circuit is chosen for a specific ripple current and saturation current. given an input voltage range and an output voltage, the inductor value and operating frequency directly determine the ripple current. the inductor ripple current in the buck mode is: d= ? ? ? ? i v fl v v l out out in ()() 1 lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. thus highest efficiency operation is obtained at low frequency with small ripple current. to achieve this how- ever, requires a large inductor. a reasonable starting point is to choose a ripple current between 20% and 40% of i o(max) . note that the largest
ltc3703-5 14 37035f appropriate breakdown specification. since most mosfets in the 30v to 60v range have logic level thresholds (v gs(min) 3 4.5v), the ltc3703-5 is designed to be used with a 4.5v to 15v gate drive supply (drv cc pin). for maximum efficiency, on-resistance r ds(on) and input capacitance should be minimized. low r ds(on) minimizes conduction losses and low input capacitance minimizes transition losses. mosfet input capacitance is a combi- nation of several components but can be taken from the typical gate charge curve included on most data sheets (figure 8). the curve is generated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. the initial slope is the effect of the gate-to-source and the gate- to-drain capacitance. the flat portion of the curve is the result of the miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. the upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to- source capacitance. the miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given v ds drain voltage, but can be adjusted for different v ds voltages by multiplying by the ratio of the application v ds to the curve specified v ds values. a way to estimate the c miller term is to take the change in gate charge from points a and b on a manufac- turers data sheet and divide by the stated v ds voltage specified. c miller is the most important selection criteria for determining the transition loss term in the top mosfet but is not directly specified on mosfet data sheets. c rss and c os are specified sometimes but definitions of these parameters are not included. when the controller is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: applicatio s i for atio wu uu mainswitchdutycycle v v synchronousswitchdutycycle vv v out in in out in = = the power dissipation for the main and synchronous mosfets at maximum output current are given by: p v v ir v i rc vv v f p vv v ir main out in max dr on in max dr miller cc th il th il sync in out in max ds n = () ++ + ? ? =+ 2 2 2 0 1 2 11 1 () ()( ) () ()() () () () () d d where d is the temperature dependency of r ds(on) , r dr is the effective top driver resistance (approximately 2 w at v gs = v miller ), v in is the drain potential and the change in drain potential in the particular application. v th(il) is the data sheet specified typical gate threshold voltage speci- fied in the power mosfet data sheet at the specified drain current. c miller is the calculated capacitance using the gate charge curve from the mosfet data sheet and the technique described above. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which peak at the highest input voltage. for v in < 25v, the high current efficiency generally improves with larger mosfets, while for v in > 25v, the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short circuit when the synchronous switch is on close to 100% of the period. the term (1 + d ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, and typically varies from 0.005/ c to 0.01/ c depending on the particular mosfet used. figure 8. gate charge characteristic + v ds v in v gs miller effect q in ab c miller = (q b ?q a )/v ds v gs v + 37035 f08
ltc3703-5 15 37035f multiple mosfets can be used in parallel to lower r ds(on) and meet the current and thermal requirements if desired. the ltc3703-5 contains large low impedance drivers capable of driving large gate capacitances without signifi- cantly slowing transition times. in fact, when driving mosfets with very low gate charge, it is sometimes helpful to slow down the drivers by adding small gate resistors (10 w or less) to reduce noise and emi caused by the fast transitions. schottky diode selection the schottky diode d1 shown in the circuit on the first page of this data sheet. conducts during the dead time between the conduction of the power mosfets. this prevents the body diode of the bottom mosfet from turning on and storing charge during the dead time and requiring a reverse recovery period that could cost as much as 1% to 2% in efficiency. a 1a schottky diode is generally a good size for 3a to 5a regulators. larger diodes result in additional losses due to their larger junction capacitance. the diode can be omitted if the efficiency loss can be tolerated. input capacitor selection in continuous mode, the drain current of the top mosfet is approximately a square wave of duty cycle v out /v in which must be supplied by the input capacitor. to prevent large input transients, a low esr input capacitor sized for the maximum rms current is given by: ii v v v v cin rms o max out in in out () () / @ ? ? ? ? 1 12 this formula has a maximum at v in = 2v out , where i rms = i o(max) /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that the ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life. this makes it advisable to further derate the capaci- tor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be placed in parallel to meet size or height requirements in the design. because tantalum and os-con capacitors are not avail- able in voltages above 30v, for regulators with input sup- plies above 30v, choice of input capacitor type is limited to ceramics or aluminum electrolytics. ceramic capacitors have the advantage of very low esr and can handle high rms current, however ceramics with high voltage ratings (>50v) are not available with more than a few microfarads of capacitance. furthermore, ceramics have high voltage coefficients which means that the capacitance values de- crease even more when used at the rated voltage. x5r and x7r type ceramics are recommended for their lower volt- age and temperature coefficients. another consideration when using ceramics is their high q which if not properly damped, may result in excessive voltage stress on the power mosfets. aluminum electrolytics have much higher bulk capacitance, however, they have higher esr and lower rms current ratings. a good approach is to use a combination of aluminum electrolytics for bulk capacitance and ceramics for low esr and rms current. if the rms current cannot be handled by the aluminum capacitors alone, when used together, the percentage of rms current that will be supplied by the aluminum capacitor is reduced to approximately: % () % , i fcr rms alum esr ? + 1 18 100 2 where r esr is the esr of the aluminum capacitor and c is the overall capacitance of the ceramic capacitors. using an aluminum electrolytic with a ceramic also helps damp the high q of the ceramic, minimizing ringing. output capacitor selection the selection of c out is primarily determined by the esr required to minimize voltage ripple. the output ripple ( d v out ) is approximately equal to: dd + ? ? ? ? v i esr fc out l out 1 8 since d i l increases with input voltage, the output ripple is highest at maximum input voltage. esr also has a signifi- cant effect on the load transient response. fast load transitions at the output will appear as voltage across the esr of c out until the feedback loop in the ltc3703-5 can applicatio s i for atio wu uu
ltc3703-5 16 37035f change the inductor current to match the new load current value. typically, once the esr requirement is satisfied the capacitance is adequate for filtering and has the required rms current rating. manufacturers such as nichicon, united chemicon and sanyo should be considered for high performance throughhole capacitors. the os-con (organic semicon- ductor dielectric) capacitor available from sanyo has the lowest product of esr and size of any aluminum electro- lytic at a somewhat higher price. an additional ceramic capacitor in parallel with os-con capacitors is recom- mended to reduce the effect of their lead inductance. in surface mount applications, multiple capacitors placed in parallel may be required to meet the esr, rms current handling and load step requirements. dry tantalum, spe- cial polymer and aluminum electrolytic capacitors are available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. several excellent surge-tested choices are the avx tps and tpsv or the kemet t510 series. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-driven applications providing that consideration is given to ripple current ratings and long term reliability. other capacitor types include pana- sonic sp and sanyo poscaps. output voltage the ltc3703-5 output voltage is set by a resistor divider according to the following formula: vv r r out =+ ? ? ? ? 08 1 1 2 . the external resistor divider is connected to the output as shown in the functional diagram, allowing remote voltage sensing. the resultant feedback signal is compared with the internal precision 800mv voltage reference by the error amplifier. the internal reference has a guaranteed tolerance of 1%. tolerance of the feedback resistors will add additional error to the output voltage. 0.1% to 1% resistors are recommended. mosfet driver supplies (drv cc and boost) the ltc3703-5 drivers are supplied from the drv cc and boost pins (see figure 2), which have an absolute maximum voltage of 15v. if the main supply voltage, v in , is higher than 15v a separate supply with a voltage between 5v and 15v must be used to power the drivers. if a separate supply is not available, one can easily be generated from the main supply using one of the circuits shown in figure 9. if the output voltage is between 5v and 15v, the output can be used to directly power the drivers as shown in figure 9a. if the output is below 5v, figure 9b shows an easy way to boost the supply voltage to a sufficient level. this boost circuit uses the lt1613 in a thinsot tm package and a chip inductor for minimal extra area (<0.2 in 2 ). two other possible schemes are an extra winding on the inductor (figure 9c) or a capacitive charge pump (figure 9d). all the circuits shown in figure 9 require a start-up circuit (q1, d1 and r1) to provide driver power at initial start-up or following a short-circuit. the resistor r1 must be sized so that it supplies sufficient base current and zener bias current at the lowest expected value of v in . when using an existing supply, the supply must be capable of supplying the required gate driver current which can be estimated from: i drvcc = (f)(q g(top) + q g(bottom) ) this equation for i drvcc is also useful for properly sizing the circuit components shown in figure 9. an external bootstrap capacitor, c b , connected to the boost pin supplies the gate drive voltage for the topside mosfets. capacitor c b is charged through external diode, d b , from the drv cc supply when sw is low. when the top side mosfet is turned on, the driver places the c b voltage across the gate-source of the top mosfet. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v drvcc . the value of the boost capacitor c b needs to be 100 times that of the total input capacitance of the top side mosfet(s). the reverse breakdown of the external diode, d b , must be greater than v in(max) . another important consideration for the external diode is the reverse recovery and reverse leakage, either of which may cause excessive reverse applicatio s i for atio wu uu thinsot is a tradmark of linear technology corporation.
ltc3703-5 17 37035f figure 9a. v cc generated from 5v < v out < 15v applicatio s i for atio wu uu v cc drv cc v in tg sw bg bgrtn ltc3703-5 v out 5v to 15v + c out 37035 f09a + c in + 1 f v in l1 5.1v v cc drv cc v in tg sw bg bgrtn ltc3703-5 v out <5v + c out 3703 f09b + c in c9 4.7 f 6.3v v in l1 5.1v c10 1 f 10v v in sw gnd shdn fb r17 37.4k 1% r17 12.1k 1% lt1613 d2 zhcs400 l2 4.7 h figure 9b. v cc generated from v out < 5v current to flow at full reverse voltage. if the reverse current times reverse voltage exceeds the maximum allowable power dissipation, the diode may be damaged. for best results, use an ultrafast recovery diode such as the mmdl770t1. an internal undervoltage lockout (uvlo) monitors the voltage on drv cc to ensure that the ltc3703-5 has sufficient gate drive voltage. if the drv cc voltage falls v cc drv cc fcb gnd v in tg1 sw bg1 bgrtn ltc3703-5 v out v sec + c out + 1 f 3703 f09c r1 v in t1 optional v cc connection 5v < v sec < 15v r2 + c in 5.1v n 1 v cc drv cc v in tg sw bg bgrtn ltc3703-5 v out + c out 3703 f09d + + c in v in (<40v) l1 1 f 5.1v bat85 bat85 bat85 vn2222ll 0.22 f figure 9c. secondary output loop and v cc connection figure 9d. capacitive charge pump for v cc (v in < 40v) below the uvlo threshold, the ltc3703-5 shuts down and the gate drive outputs remain low. bottom mosfet source supply (bgrtn) the bottom gate driver, bg, switches from drv cc to bgrtn where bgrtn can be a voltage between ground and C5v. why not just keep it simple and always connect bgrtn to ground? in high voltage switching converters, the switch
ltc3703-5 18 37035f node dv/dt can be many volts/ns, which will pull up on the gate of the bottom mosfet through its miller capacitance. if this miller current, times the internal gate resistance of the mosfet plus the driver resistance, exceeds the thresh- old of the fet, shoot-through will occur. by using a nega- tive supply on bgrtn, the bg can be pulled below ground when turning the bottom mosfet off. this provides a few extra volts of margin before the gate reaches the turn-on threshold of the mosfet. be aware that the maximum voltage difference between drv cc and bgrtn is 15v. if, for example, v bgrtn = C2v, the maximum voltage on drv cc pin is now 13v instead of 15v. current limit programming programming current limit on the ltc3703-5 is straight forward. the i max pin sets the current limit by setting the maximum allowable voltage drop across the bottom mosfet. the voltage across the mosfet is set by its on- resistance and the current flowing in the inductor, which is the same as the output current. the ltc3703-5 current limit circuit inverts the negative voltage across the mosfet before comparing it to the voltage at i max , allowing the current limit to be set with a positive voltage. to set the current limit, calculate the expected voltage drop across the bottom mosfet at the maximum desired current and maximum junction temperature: v prog = (i limit )(r ds(on) )( 1 + d ) where d is explained in the mosfet selection section. v prog is then programmed at the i max pin using the internal 12 m a pull-up and an external resistor: r imax = v prog /12 m a the current limit value should be checked to ensure that i limit(min) > i out(max) . the minimum value of current limit generally occurs with the largest v in at the highest ambi- ent temperature, conditions that cause the largest power loss in the converter. note that it is important to check for self-consistency between the assumed mosfet junction temperature and the resulting value of i limit which heats the mosfet switches. caution should be used when setting the current limit based upon the r ds(on) of the mosfets. the maximum current limit is determined by the minimum mosfet on- resistance. data sheets typically specify nominal and maximum values for r ds(on) , but not a minimum. a reasonable assumption is that the minimum r ds(on) lies the same amount below the typical value as the maximum lies above it. consult the mosfet manufacturer for further guidelines. for best results, use a v prog voltage between 100mv and 500mv. values outside of this range may give less accu- rate current limit. the current limit can also be disabled by floating the i max pin. feedback loop/compensation feedback loop types in a typical ltc3703-5 circuit, the feedback loop consists of the modulator, the external inductor, the output capaci- tor and the feedback amplifier with its compensation network. all of these components affect loop behavior and must be accounted for in the loop compensation. the modulator consists of the internal pwm generator, the output mosfet drivers and the external mosfets them- selves. from a feedback loop point of view, it looks like a linear voltage transfer function from comp to sw and has a gain roughly equal to the input voltage. it has fairly benign ac behavior at typical loop compensation frequen- cies with significant phase shift appearing at half the switching frequency. the external inductor/output capacitor combination makes a more significant contribution to loop behavior. these components cause a second order lc roll off at the output, with the attendant 180 phase shift. this rolloff is what filters the pwm waveform, resulting in the desired dc output voltage, but the phase shift complicates the loop compen- sation if the gain is still higher than unity at the pole fre- quency. eventually (usually well above the lc pole frequency), the reactance of the output capacitor will ap- proach its esr and the rolloff due to the capacitor will stop, leaving 6db/octave and 90 of phase shift (figure 10). so far, the ac response of the loop is pretty well out of the users control. the modulator is a fundamental piece of the ltc3703-5 design and the external l and c are usually chosen based on the regulation and load current require- ments without considering the ac loop response. the applicatio s i for atio wu uu
ltc3703-5 19 37035f for an extended frequency range. ltc3703-5 circuits using conventional switching grade electrolytic output capacitors can often get acceptable phase margin with type 2 compensation. type 3 loops (figure 13) use two poles and two zeros to obtain a 180 phase boost in the middle of the frequency band. a properly designed type 3 circuit can maintain acceptable loop stability even when low output capacitor esr causes the lc section to approach 180 phase shift well above the initial lc roll-off. as with a type 2 circuit, the loop should cross through 0db in the middle of the phase bump to maximize phase margin. many ltc3703-5 circuits using low esr tantalum or os-con output capaci- tors need type 3 compensation to obtain acceptable phase margin with a high bandwidth feedback loop. feedback amplifier, on the other hand, gives us a handle with which to adjust the ac response. the goal is to have 180 phase shift at dc (so the loop regulates) and some- thing less than 360 phase shift at the point that the loop gain falls to 0db. the simplest strategy is to set up the feedback amplifier as an inverting integrator, with the 0db frequency lower than the lc pole (figure 11). this type 1 configuration is stable but transient response is less than exceptional if the lc pole is at a low frequency. applicatio s i for atio wu uu gain (db) 37035 f10 a v 0 phase 6db/oct ?2db/oct gain phase (deg) freq ?0 180 270 360 figure 10. transfer function of buck modulator gain (db) 37035 f11 0 phase 6db/oct gain phase (deg) freq ?0 180 270 360 r b r1 fb c1 in out + v ref figure 11. type 1 schematic and transfer function gain (db) 37035 f12 0 phase 6db/oct 6db/oct gain phase (deg) freq ?0 ?80 ?70 ?60 r b v ref r1 r2 fb c2 in out + c1 figure 12. type 2 schematic and transfer function gain (db) 37035 f13 0 phase 6db/oct +6db/oct 6db/oct gain phase (deg) freq ?0 180 270 360 r b v ref r1 r2 fb c2 in out + c1 c3 r3 figure 13. type 3 schematic and transfer function figure 12 shows an improved type 2 circuit that uses an additional pole-zero pair to temporarily remove 90 of phase shift. this allows the loop to remain stable with 90 more phase shift in the lc section, provided the loop reaches 0db gain near the center of the phase bump. type 2 loops work well in systems where the esr zero in the lc roll-off happens close to the lc pole, limiting the total phase shift due to the lc. the additional phase compensation in the feedback amplifier allows the 0db point to be at or above the lc pole frequency, improving loop bandwidth substantially over a simple type 1 loop. it has limited ability to compensate for lc combinations where low capacitor esr keeps the phase shift near 180 feedback component selection selecting the r and c values for a typical type 2 or type 3 loop is a nontrivial task. the applications shown in this data sheet show typical values, optimized for the power components shown. they should give acceptable perfor- mance with similar power components, but can be way off
ltc3703-5 20 37035f if even one major power component is changed signifi- cantly. applications that require optimized transient re- sponse will require recalculation of the compensation values specifically for the circuit in question. the underly- ing mathematics are complex, but the component values can be calculated in a straightforward manner if we know the gain and phase of the modulator at the crossover frequency. modulator gain and phase can be measured directly from a breadboard or can be simulated if the appropriate parasitic values are known. measurement will give more accurate results, but simulation can often get close enough to give a working system. to measure the modulator gain and phase directly, wire up a breadboard with an ltc3703-5 and the actual mosfets, inductor and input and output capacitors that the final design will use. this breadboard should use appropriate construction techniques for high speed analog circuitry: bypass capacitors located close to the ltc3703-5, no long wires connecting components, appropriately sized ground returns, etc. wire the feedback amplifier as a simple type 1 loop, with a 10k resistor from v out to fb and a 0.1 m f feedback capacitor from comp to fb. choose the bias resistor (r b ) as required to set the desired output voltage. disconnect r b from ground and connect it to a signal generator or to the source output of a network analyzer (figure 14) to inject a test signal into the loop. measure the gain and phase from the comp pin to the output node at the positive terminal of the output capacitor. make sure the analyzers input is ac coupled so that the dc voltages present at both the comp and v out applicatio s i for atio wu uu nodes dont corrupt the measurements or damage the analyzer. if breadboard measurement is not practical, a spice simulation can be used to generate approximate gain/ phase curves. plug the expected capacitor, inductor and mosfet values into the following spice deck and gener- ate an ac plot of v(v out )/v(comp) in db and phase of v out in degrees. refer to your spice manual for details of how to generate this plot. *3703-5 modulator gain/phase *2003 linear technology *this file written to run with pspice 8.0 *may require modifications for other spice simulators *mosfets rfet mod sw 0.02 ;mosfet rdson *inductor lext sw out1 10u ;inductor value rl out1 out 0.015 ;inductor series r *output cap cout out out2 540u ;capacitor value resr out2 0 0.01 ;capacitor esr *3703-5 internals emod mod 0 value = {43*v(comp)} ;3703-5multiplier vstim comp 0 0 ac 1 ;ac stimulus .ac dec 100 1k 1meg .probe .end with the gain/phase plot in hand, a loop crossover fre- quency can be chosen. usually the curves look something like figure 10. choose the crossover frequency in the rising or flat parts of the phase curve, beyond the external lc poles. frequencies between 10khz and 50khz usually work well. note the gain (gain, in db) and phase (phase, in degrees) at this point. the desired feedback amplifier gain will be Cgain to make the loop gain at 0db at this frequency. now calculate the needed phase boost, assum- ing 60 as a target phase margin: boost = C (phase + 30 ) if the required boost is less than 60 , a type 2 loop can be used successfully, saving two external components. v in tg sw bg inv mode/sync comp fb run/ss ltc3703-5 v cc c in 5v v in m1 v out to analyzer v comp to analyzer ac source from analyzer l ext m2 10 f drv cc f set 0.1 f r b boost gnd bgrtn + + 10k nc c out 37035 f14 + figure 14. modulator gain/phase measurement set-up
ltc3703-5 21 37035f boost values greater than 60 usually require type 3 loops for satisfactory performance. finally, choose a convenient resistor value for r1 (10k is usually a good value). now calculate the remaining values: (k is a constant used in the calculations) f = chosen crossover frequency g = 10 (gain/20) (this converts gain in db to g in absolute gain) type 2 loop: type 3 loop: applicatio s i for atio wu uu boost converter design the following sections discuss the use of the ltc3703-5 as a step-up (boost) converter. in boost mode, the ltc3703-5 can step-up output voltages as high as 60v. these sections discuss only the design steps specific to a boost converter. for the design steps common to both a buck and a boost, see the applicable section in the buck mode section. an example of a boost converter circuit is shown in the typical applications section. to operate the ltc3703-5 in boost mode, the inv pin should be tied to the v cc voltage (or a voltage above 2v). note that in boost mode, pulse-skip operation and the line feedforward com- pensation are disabled. for a boost converter, the duty cycle of the main switch is: d vv v out in out = for high v out to v in ratios, the maximum v out is limited by the ltc3703-5s maximum duty cycle which is typically 93%. the maximum output voltage is therefore: v v d v out max in min max in min () () () =@ 1 14 boost converter: inductor selection in a boost converter, the average inductor current equals the average input current. thus, the maximum average inductor current can be calculated from: i i d i v v lmax omax max omax o in min () () () () = - = 1 similar to a buck converter, choose the ripple current to be 20% to 40% of i l(max) . the ripple current amplitude then determines the inductor value as follows: l v if d in min l max = d () the minimum required saturation current for the inductor is: i l(sat) > i l(max) + d i l /2 k boost c fgkr cck r k fc r vr vv b ref out ref =+ ? ? ? ? = =- () = = - tan () 2 45 2 1 21 12 1 2 21 1 2 p p k boost c fgr cck r k fc r r k c fkr r vr vv b ref out ref =+ ? ? ? ? = =- () = = - = = - tan () 2 4 45 2 1 21 12 1 2 21 3 1 1 3 1 23 1 p p p
ltc3703-5 22 37035f boost converter: power mosfet selection for information about choosing power mosfets for a boost converter, see the power mosfet selection sec- tion for the buck converter, since mosfet selection is similar. however, note that the power dissipation equa- tions for the mosfets at maximum output current in a boost converter are: pd i d r v i d rc vv v f p d ir main max max max ds on out max max dr miller cc th il th il sync max max ds on = ? ? ? ? + () + ? ? ? ? ()( ) + ? ? () = ? ? ? ? () + () 1 1 1 21 11 1 1 1 2 2 2 () () () () d d boost converter: output capacitor selection in boost mode, the output capacitor requirements are more demanding due to the fact that the current waveform is pulsed instead of continuous as in a buck converter. the choice of component(s) is driven by the acceptable ripple voltage which is affected by the esr, esl and bulk capacitance as shown in figure 15. the total output ripple voltage is: d= + ? ? ? ? vi fc esr d out o max out max () 1 1 where the first term is due to the bulk capacitance and second term due to the esr. the choice of output capacitor is driven also by the rms ripple current requirement. the rms ripple current is: ii vv v rms cout o max o in min in min ()() () () ? at lower output voltages (less than 30v), it may be possible to satisfy both the output ripple voltage and rms ripple current requirements with one or more capacitors of applicatio s i for atio wu uu figure 15. output voltage ripple waveform for a boost converter ringing due to total inductance (board + cap) ? v esr ? v cout v out (ac) a single capacitor type. however, at output voltages above 30v where capacitors with both low esr and high bulk capacitance are hard to find, the best approach is to use a combination of aluminum and ceramic capacitors (see discussion in input capacitor section for the buck con- verter). with this combination, the ripple voltage can be improved significantly. the low esr ceremic capacitor will minimize the esr step, while the electrolytic will supply the required bulk capacitance. boost converter: input capacitor selection the input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input and the input current waveform is continuous. the input voltage source impedance deter- mines the size of the input capacitor, which is typically in the range of 10 m f to 100 m f. a low esr capacitor is recommended though not as critical as for the output capacitor. the rms input capacitor ripple current for a boost con- verter is: i v lf d rms cin in min max () () . = 03 please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter and solid tantalum capacitors can fail catastrophically under these conditions. be sure to specify surge-tested capacitors! boost converter: current limit programming the ltc3703-5 provides current limiting in boost mode by monitoring the v ds of the main switch during its on-time and comparing it to the voltage at i max . to set the current limit, calculate the expected voltage drop across the mosfet at the maximum desired inductor current and
ltc3703-5 23 37035f maximum junction temperature. the maximum inductor current is a function of both duty cycle and maximum load current, so the limit must be set for the maximum expected duty cycle (minimum v in ) in order to ensure that the current limit does not kick in at loads < i o(max) : v i d r v v ir prog omax max ds on out in min o max ds on =+ = ? ? ? ? + () () () () () () () 1 1 1 d d once v prog is determined, r imax is chosen as follows: r imax = v prog /12 m a note that in a boost mode architecture, it is only possible to provide protection for soft shorts where v out > v in . for hard shorts, the inductor current is limited only by the input supply capability. refer to current limit program- ming for buck mode for further considerations for current limit programming. boost converter: feedback loop/compensation compensating a voltage mode boost converter is unfortu- nately more difficult than for a buck converter. this is due to an additional right-half plane (rhp) zero that is present in the boost converter but not in a buck. the additional phase lag resulting from the rhp zero is difficult if not impossible to compensate even with a type 3 loop, so the best approach is usually to roll off the loop gain at a lower frequency than what could be achievable in buck converter. a typical gain/phase plot of a voltage-mode boost con- verter is shown in figure 16. the modulator gain and phase can be measured as described for a buck converter or can be estimated as follows: gain (comp-to-v out dc gain) = 20log(v out 2 /v in ) dominant pole: f p = v v lc in out 1 2 p since significant phase shift begins at frequencies above the dominant lc pole, choose a crossover frequency no greater than about half this pole frequency. the gain of the compensation network should equal Cgain at this fre- quency so that the overall loop gain is 0db here. the compensation component to achieve this, using a type 1 amplifier (see figure 11), is: g = 10 Cgain/20 c1 = 1/(2 p ? f ? g ? r1) run/soft-start function the run/ss pin is a multipurpose pin that provide a soft- start function and a means to shut down the ltc3703-5. soft-start reduces the input supplys surge current by gradually increasing the duty cycle and can also be used for power supply sequencing. pulling run/ss below 1v puts the ltc3703-5 into a low quiescent current shutdown (i q @ 25 m a). this pin can be driven directly from logic as shown in figure 17. releasing applicatio s i for atio wu u u figure 16. transfer function of boost modulator gain (db) phase (deg) 37035 f16 a v 00 ?0 180 phase gain ?2db/oct figure 17. ltc3703-5 startup operation 2ms/div v out 5v/div v in = 50v i load = 2a c ss = 0.01 f run/ss 2v/div i l 2a/div 37035 f17
ltc3703-5 24 37035f the main output voltage and the turns ratio of the extra winding to the primary winding as follows: v sec ? (n + 1)v out since the secondary winding only draws current when the synchronous switch is on, load regulation at the auxiliary output will be relatively good as long as the main output is running in continuous mode. as the load on the primary output drops and the ltc3703-5 switches to pulse skip mode operation, the auxiliary output may not be able to maintain regulation, especially if the load on the auxiliary output remains heavy. to avoid this, the auxiliary output voltage can be divided down with a conventional feedback resistor string with the divided auxiliary output voltage fed back to the mode/sync pin. the mode/sync threshold is trimmed to 800mv with 20mv of hysteresis, allowing precise control of the auxiliary voltage and is set as follows: vv r r sec min () . ?+ ? ? ? ? 08 1 1 2 where r1 and r2 are shown in figure 9c. if the ltc3703-5 is operating in pulse skip mode and the auxiliary output voltage drops below v sec(min) , the mode/ sync pin will trip and the ltc3703-5 will resume continu- ous operation regardless of the load on the main output. thus, the mode/sync pin removes the requirement that power must be drawn from the inductor primary in order to extract power from the auxiliary winding. with the loop in continuous mode (mode/sync < 0.8v), the auxiliary outputs may nominally be loaded without regard to the primary output load. the following table summarizes the possible states avail- able on the mode/sync pin: table 1. mode/sync pin condition dc voltage: 0v to 0.75v forced continuous current reversal enabled dc voltage: 3 0.87v pulse skip mode operation no current reversal feedback resistors regulating a secondary winding ext. clock: 0v to 3 2v forced continuous no current reversal the run/ss pin allows an internal 4 m a current source to charge up the soft-start capacitor c ss . when the voltage on run/ss reaches 1v, the ltc3703-5 begins operating at its minimum on-time. as the run/ss voltage increases from 1v to 3v, the duty cycle is allowed to increase from 0% to 100%. the duty cycle control minimizes input supply inrush current and elimates output voltage over- shoot at start-up and ensures current limit protection even with a hard short. the run/ss voltage is internally clamped at 4v. if run/ss starts at 0v, the delay before starting is approximately: t v a csfc delay start ss ss , (. / ) = m =m 1 4 025 plus an additional delay, before the output will reach its regulated value, of: t vv a csfc delay reg ss ss , (. / ) 3 m =m 31 4 05 the start delay can be reduced by using diode d1 in figure 18. figure 18. run/ss pin interfacing applicatio s i for atio wu uu 3.3v or 5v run/ss d1 c ss 37035 f18 run/ss c ss mode/sync pin (operating mode and secondary winding control) the mode/sync pin is a dual function pin that can be used for enabling or disabling pulse skip mode operation and also as an external clock input for synchronizing the inter- nal oscillator (see next section). pulse skip mode is enabled when the mode/sync pin is above 0.8v and is disabled, i.e. forced continuous, when the pin is below 0.8v. in addition to providing a logic input to force continuous operation and external synchronization, the mode/sync pin provides a means to regulate a flyback winding output as shown in figure 9c. the auxiliary output is taken from a second winding on the core of the inductor, converting it to a transformer. the auxiliary output voltage is set by
ltc3703-5 25 37035f mode/sync pin (external synchronization) the internal ltc3703-5 oscillator can be synchronized to an external oscillator by applying and clocking the mode/ sync pin with a signal above 2v p-p . the internal oscillator locks to the external clock after the second clock transi- tion is received. when external synchronization is de- tected, ltc3703-5 will operate in forced continuous mode. if an external clock transition is not detected for three successive periods, the internal oscillator will revert to the frequency programmed by the r set resistor. the internal oscillator can synchronize to frequencies be- tween 100khz and 600khz, independent of the frequency programmed by the r set resistor. however, it is recom- mended that an r set resistor be chosen such that the frequency programmed by the r set resistor is close to the expected frequency of the external clock. in this way, the best converter operation (ripple, component stress, etc) is achieved if the external clock signal is lost. minimum on-time considerations (buck mode) minimum on-time t on(min) is the smallest amount of time that the ltc3703-5 is capable of turning the top mosfet on and off again. it is determined by internal timing delays and the amount of gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t v vf t on out in on min => () where t on(min) is typically 200ns. if the duty cycle falls below what can be accommodated by the minimum on-time, the ltc3703-5 will begin to skip cycles. the output will be regulated, but the ripple current and ripple voltage will increase. if lower frequency opera- tion is acceptable, the on-time can be increased above t on(min) for the same step-down ratio. pin clearance/creepage considerations the ltc3703-5 is available in two packages (gn16 and g28) both with identical functionality. the gn16 package gives the smallest size solution, however the 0.013 (minimum) space between pins may not provide sufficient applicatio s i for atio wu u u pc board trace clearance between high and low voltage pins in higher voltage applications. where clearance is an issue, the g28 package should be used. the g28 package has 4 unconnected pins between the all adjacent high voltage and low voltage pins, providing 5(0.0106) = 0.053 clearance which will be sufficient for most applica- tions up to 60v. for more information, refer to the printed circuit board design standards described in ipc-2221 (www.ipc.org). efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power (x100%). per- cent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentage of input power. it is often useful to analyze the individual losses to determine what is limiting the efficiency and what change would produce the most improvement. al- though all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3703-5 circuits: 1) ltc3703-5 v cc current, 2) mosfet gate current, 3) i 2 r losses, 4) topside mosfet transition losses. 1. v cc supply current. the v cc current is the dc supply current given in the electrical characteristics table which powers the internal control circuitry of the ltc3703-5. total supply current is typically about 2.5ma and usually results in a small (<1%) loss which is proportional to v cc . 2. drv cc current is mosfet driver current. this current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched on and then off, a packet of gate charge q g moves from drv cc to ground. the resulting dq/dt is a current out of the drv cc supply. in continuous mode, i drvcc = f(q g(top) + q g(bot) ), where q g(top) and q g(bot) are the gate charges of the top and bottom mosfets. 3. i 2 r losses are predicted from the dc resistances of mosfets, the inductor and input and output capacitor esr. in continuous mode, the average output current flows through l but is chopped between the topside
ltc3703-5 26 37035f mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the dcr resistance of l to obtain i 2 r losses. for example, if each r ds(on) = 25m w and r l = 25m w , then total resis- tance is 50m w . this results in losses ranging from 1% to 5% as the output current increases from 1a to 5a for a 5v output. 4. transition losses apply only to the topside mosfet in buck mode and they become significant when operating at higher input voltages (typically 20v or greater). transition losses can be estimated from the second term of the p main equation found in the power mosfet selection section. the transition losses can become very significant at the high end of the ltc3703-5 operating voltage range. to improve efficiency, one may consider lowering the fre- quency and/or using mosfets with lower c rss at the expense of higher r ds(on) . other losses including c in and c out esr dissipative losses, schottky conduction losses during dead-time, and inductor core losses generally account for less than 2% total additional loss. transient response due to the high gain error amplifier and line feedforward compensation of the ltc3703-5, the output accuracy due to dc variations in input voltage and output load current will be almost negligible. for the few cycles following a load transient, however, the output deviation may be larger while the feedback loop is responding. consider a typical 48v input to 5v output application circuit, subjected to a 1a to 5a load transient. initially, the loop is in regulation and the dc current in the output capacitor is zero. suddenly, an extra 4a (= 5a-1a) flows out of the output capacitor while the inductor is still supplying only 1a. this sudden change will generate a (4a) ? (r esr ) voltage step at the output; with a typical 0.015 w output capacitor esr, this is a 60mv step at the output. the feedback loop will respond and will move at the band- width allowed by the external compensation network towards a new duty cycle. if the unity gain crossover fre- quency is set to 50khz, the comp pin will get to 60% of the way to 90% duty cycle in 3 m s. now the inductor is seeing 43v across itself for a large portion of the cycle and its current will increase from 1a at a rate set by di/dt = v/l. if the inductor value is 10 m h, the peak di/dt will be 43v/10 m h or 4.3a/ m s. sometime in the next few micro-seconds after the switch cycle begins, the inductor current will have risen to the 5a level of the load current and the output voltage will stop dropping. at this point, the inductor cur- rent will rise somewhat above the level of the output cur- rent to replenish the charge lost from the output capacitor during the load transient. with a properly compensated loop, the entire recovery time will be inside of 10 m s. most loads care only about the maximum deviation from ideal, which occurs somewhere in the first two cycles after the load step hits. during this time, the output capacitor does all the work until the inductor and control loop regain control. the initial drop (or rise if the load steps down) is entirely controlled by the esr of the capacitor and amounts to most of the total voltage drop. to minimize this drop, choose a low esr capacitor and/or parallel multiple ca- pacitors at the output. the capacitance value accounts for the rest of the voltage drop until the inductor current rises. with most output capacitors, several devices paralleled to get the esr down will have so much capacitance that this drop term is negligible. ceramic capacitors are an excep- tion; a small ceramic capacitor can have suitably low esr with relatively small values of capacitance, making this second drop term more significant. optimizing loop compensation loop compensation has a fundamental impact on tran- sient recovery time, the time it takes the ltc3703-5 to recover after the output voltage has dropped due to a load step. optimizing loop compensation entails maintaining the highest possible loop bandwidth while ensuring loop stability. the feedback component selection section de- scribes in detail the techniques used to design an opti- mized type 3 feedback loop, appropriate for most ltc3703-5 systems. applicatio s i for atio wu u u
ltc3703-5 27 37035f measurement techniques measuring transient response presents a challenge in two respects: obtaining an accurate measurement and gener- ating a suitable transient to test the circuit. output mea- surements should be taken with a scope probe directly across the output capacitor. proper high frequency prob- ing techniques should be used. in particular, dont use the 6" ground lead that comes with the probe! use an adapter that fits on the tip of the probe and has a short ground clip to ensure that inductance in the ground path doesnt cause a bigger spike than the transient signal being measured. conveniently, the typical probe tip ground clip is spaced just right to span the leads of a typical output capacitor. now that we know how to measure the signal, we need to have something to measure. the ideal situation is to use the actual load for the test and switch it on and off while watching the output. if this isnt convenient, a current step generator is needed. this generator needs to be able to turn on and off in nanoseconds to simulate a typical switching logic load, so stray inductance and long clip leads between the ltc3703-5 and the transient generator must be minimized. figure 19 shows an example of a simple transient genera- tor. be sure to use a noninductive resistor as the load elementmany power resistors use an inductive spiral pattern and are not suitable for use here. a simple solution is to take ten 1/4w film resistors and wire them in parallel to get the desired value. this gives a noninductive resistive load which can dissipate 2.5w continuously or 50w if pulsed with a 5% duty cycle, enough for most ltc3703-5 circuits. solder the mosfet and the resistor(s) as close to the output of the ltc3703-5 circuit as possible and set up the signal generator to pulse at a 100hz rate with a 5% duty cycle. this pulses the ltc3703-5 with 500 m s transients10ms apart, adequate for viewing the entire transient recovery time for both positive and negative transitions while keeping the load resistor cool. design example as a design example, take a supply with the following specifications: v in = 20v to 60v (48v nominal), v out = 12v 5%, i out(max) = 10a, f=250khz. first, calculate r set to give the 250khz operating frequency: r set = 7100/(250-25) = 31.6k next, choose the inductor value for about 40% ripple current at maximum v in : l v khz a h = ? ? ? ? =m 12 250 0 4 10 1 12 60 10 ( )( . )( ) with 10 m h inductor, ripple current will vary from 1.9a to 3.8a (19% to 38%) over the input supply range. next, verify that the minimum on-time is not violated. the minimum on-time occurs at maximum v in : t v v f khz ns on min out in min () () () ( ) == = 12 60 250 800 which is above the ltc3703-5s 200ns minimum on-time. next, choose the top and bottom mosfet switch. since the drain of each mosfet will see the full supply voltage 60v(max) plus any ringing, choose a 60v mosfet. si7850dp has a 60v bv dss , r ds(on) = 22m w (max), d = 0.007/ c, c miller = (9nc C 3nc)/30v = 200pf, v gs(miller) = 3.8v, q ja = 20 c/w. the power dissipation can be applicatio s i for atio wu u u figure 19. transient load generator ltc3703-5 v out irfz44 or equivalent r load 50 0v to 10v 100hz, 5% duty cycle locate close to the output 37035 f19 pulse generator
ltc3703-5 28 37035f estimated at maximum input voltage, assuming a junction temperature of 100 c (30 c above an ambient of 70 c): p pf k www main =+ [] + ? ? ? ? + ? ? ? ? =+= 12 60 10 1 0 007 100 25 0 022 60 10 2 2 200 1 10 3 8 1 38 250 067 076 143 2 2 () . ( )(. ) () ()( ) . . () ... and double check the assumed t j in the mosfet: t j = 70 c + (1.43w)(20 c/w) = 99 c since the synchronous mosfet will be conducting over twice as long each period (almost 100% of the period in short circuit) as the top mosfet, use two si7850dp mosfets on the bottom: p w sync = - ? ? ? ? + [] ? ? ? ? = 60 12 60 10 1 0 007 100 25 0 022 2 134 2 () . ( ) . . t j = 70 c + (1.34w)(20 c/w) = 97 c next, set the current limit resistor. since i max = 10a, the limit should be set such that the minimum current limit is >10a. minimum current limit occurs at maximum r ds(on) . using the above calculation for bottom mosfet t j , the max r ds(on) = (22m w /2) [1 + 0.007 (97-25)] = 16.5m w therefore, i max pin voltage should be set to (10a)(0.0165) = 0.165v. the r set resistor can now be chosen to be 0.165v/12 m a = 14k w . c in is chosen for an rms current rating of about 5a (i max /2) at 85 c. for the output capacitor, two low esr oscon capacitors (18m w each) are used to minimize output voltage changes due to inductor current ripple and load steps. the ripple voltage will be: d v out(ripple) = d i l(max) (esr) = (4a)(0.018 w /2) = 36mv however, a 0a to 10a load step will cause an output voltage change of up to: d v out(step) = d i load(esr) = (10a)(0.009 w ) = 90mv pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3703-5. these items are also illustrated graphically in the layout diagram of figure 20. for layout of a boost mode converter, layout is similar with v in and v out swapped. check the following in your layout: 1. keep the signal and power grounds separate. the signal ground consists of the ltc3703-5 gnd pin, the ground return of c vcc , and the (C) terminal of v out . the power ground consists of the schottky diode anode, the source of the bottom side mosfet, and the (C) terminal of the input capacitor and drv cc capacitor. connect the signal and power grounds together at the (C) terminal of the output capacitor. also, try to connect the (C) terminal of the output capacitor as close as possible to the (C) terminals of the input and drv cc capacitor and away from the schottky loop described in (2). 2. the high di/dt loop formed by the top n-channel mosfet, the bottom mosfet and the c in capacitor should have short leads and pc trace lengths to minimize high frequency noise and voltage stress from inductive ringing. 3. connect the drain of the top side mosfet directly to the (+) plate of c in , and connect the source of the bottom side mosfet directly to the (C) terminal of c in . this capacitor provides the ac current to the mosfets. 4. place the ceramic c drvcc decoupling capacitor imme- diately next to the ic, between drv cc and bgrtn. this capacitor carries the mosfet drivers current peaks. likewise the c b capacitor should also be next to the ic between boost and sw. applicatio s i for atio wu u u
ltc3703-5 29 37035f applicatio s i for atio wu u u figure 20. ltc3703-5 buck converter suggested layout ltc3703-5 mode/sync fset comp fb i max inv run/ss gnd v in boost tg sw v cc drv cc bg bgrtn 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c c1 c in c c2 c c3 r c1 r c2 r1 r2 r f r max r set c b v in m1 m2 l1 d1 v out c out d b v cc c ss 37035 f18 c drvcc x5r c vcc x5r + + + 5. place the small-signal components away from high frequency switching nodes (boost, sw, tg, and bg). in the layout shown in figure 20, all the small signal compo- nents have been placed on one side of the ic and all of the power components have been placed on the other. this also helps keep the signal ground and power ground isolated. 6. a separate decoupling capacitor for the supply, v cc , is useful with an rc filter between the drv cc supply and v cc pin to filter any noise injected by the drivers. connect this capacitor close to the ic, between the v cc and gnd pins and keep the ground side of the v cc capacitor (signal ground) isolated from the ground side of the drv cc capacitor (power ground). 7. for optimum load regulation and true remote sensing, the top of the output resistor divider should connect independently to the top of the output capacitor (kelvin connection), staying away from any high dv/dt traces. place the divider resistors near the ltc3703-5 in order to keep the high impedance fb node short. 8. for applications with multiple switching power convert- ers connected to the same input supply, make sure that the input filter capacitor for the ltc3703-5 is not shared with other converters. ac input current from another converter could cause substantial input voltage ripple, and this could interfere with the operation of the ltc3703-5. a few inches of pc trace or wire (l @ 100nh) between c in of the ltc3703-5 and the actual source v in should be sufficient to prevent input noise interference problems.
ltc3703-5 30 37035f single input supply 5v/5a output step-down converter typical applicatio s u 15v-60v input voltage to 12v/10a step-down converter with pulse skip mode enabled ltc3703-5 mode/sync fset comp fb i max inv run/ss gnd 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v in boost tg sw v cc drv cc bg bgrtn c in 22 f 100v 2 c c2 1000pf c c3 2200pf r c1 10k r max 15k c c1 470pf r c2 100 r1 113k 1% r2 8.06k 1% r f 10 r set 25k c b 0.1 f v in 15v to 60v m2 si7460dp l1 8 h d1 mbr1100 v out 12v 10a c out 220 f 25v 2 d b mmdl770t1 v cc 5v to 15v c ss 0.1 f 37035 ta01 c drvcc 10 f c vcc 1 f + + + m1 si7850dp 22 f 25v ltc3703-5 mode/sync fset comp fb i max inv run/ss gnd v in boost tg sw v cc drv cc bg bgrtn c in 22 f 100v v in 6v to 60v c c2 1000pf c c3 2200pf r c1 10k r max 15k r c2 100 *optional zener provides undervoltage lockout on input supply, v uvlo @ 5 + v z r1 113k 1% r2 21.5k 1% r f 10 r set 25k c b 0.1 f m2 si7850dp l1 4.7 h d1 mbr1100 v out 5v 5a c out 220 f 25v d b1 mmdl770t1 c ss 0.1 f 3703 ta02 c drvcc 10 f c vcc 1 f + + + m1 si7850dp 22 f 25v fzt600 100 10k * 5.1v cmdsh-3 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 c c1 470pf 4.7 d b2 mmdl770t1
ltc3703-5 31 37035f gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) u package descriptio g package 28-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .0532 ?.0688 (1.35 ?1.75) .008 ?.012 (0.203 ?0.305) typ .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale g28 ssop 0204 0.09 ?0.25 (.0035 ?.010) 0 ?8 0.55 ?0.95 (.022 ?.037) 5.00 ?5.60** (.197 ?.221) 7.40 ?8.20 (.291 ?.323) 1234 5 6 7 8 9 10 11 12 14 13 9.90 ?10.50* (.390 ?.413) 25 26 22 21 20 19 18 17 16 15 23 24 27 28 2.0 (.079) max 0.05 (.002) min 0.65 (.0256) bsc 0.22 ?0.38 (.009 ?.015) typ millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 ?5.7 7.8 ?8.2 recommended solder pad layout 1.25 0.12
ltc3703-5 32 37035f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2004 lt/tp 0404 1k ? printed in usa related parts typical applicatio u part number description comments lt1074hv/lt1076hv monolithic 5a/2a step-down dc/dc converters v in up to 60v, to-220 and dd packages lt1339 high power synchronous dc/dc controller v in up to 60v, drivers 10,000pf gate capacitance, i out 20a ltc1702a dual, 2-phase synchronous dc/dc controller 550khz operation, no r sense , 3v v in 7v, i out 20a ltc1735 synchronous step-down dc/dc controller 3.5v v in 36v, 0.8v v out 6v, current mode, i out 20a ltc1778 no r sense synchronous dc/dc controller 4v v in 36v, fast transient response, current mode, i out 20a lt1956 monolithic 1.5a, 500khz step-down regulator 5.5v v in 60v, 2.5ma supply current, 16-pin ssop lt3010 50ma, 3v to 80v linear regulator 1.275v v out 60v, no protection diode required, 8-lead msop lt3430/lt3431 monolithic 3a, 200khz/500khz step-down regulator 5.5v v in 60v, 0.1 w saturation switch, 16-pin ssop lt3433 monolithic step-up/step-down dc/dc converter 4v v in 60v, 500ma switch, automatic step-up/step-down, single inductor ltc ? 3703 100v synchronous dc/dc controller v in up to 100v, 9.3v to 15v gate drive supply 5v to 24v/5a synchronous boost converter ltc3703-5 mode/sync fset comp fb i max inv run/ss gnd v in boost tg sw v cc drv cc bg bgrtn c out 220 f 30v 3 r max 15k 0.1 f c c1 100pf 10k r2 3.92k 1% r f 10 r1 113k 1% r set 25k c b 0.1 f m2 si7892dp l1 3.3 h mbrs140t3 v in 4.5v to 15v v out 24v 5a c in 100 f 20v d b cmdsh-3 c ss 0.1 f 37035 ta03 c drvcc 10 f c vcc 1 f + + + m1 si7390dp 22 f 25v 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8

▲Up To Search▲

Price & Availability of LTC3703EGN-5

	To Download LTC3703EGN-5 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .